25/12/2025
Launch Your Engineering New Career with Grovf.
Grovf is proud to announce the next edition of its free Grow With Grovf – Internships & Trainings program, designed for students in radiophysics, IT, engineering, and informatics.
Training Topics
- Fundamentals of Digital Electronics Design
- RTL Design using the SystemVerilog language
- Verification Principles for Digital Systems
- Universal Verification Methodology (UVM)
- SystemVerilog for Verification
- FPGA Basics: From Theory to Practice
Main Requirements
- Background in mathematics, electronics, and programming
- Basic knowledge of algorithms and C/C++
- Working knowledge of Linux
- Knowledge of Verilog / SystemVerilog will be considered an advantage
- Knowledge of English and Russian is a plus
Program Details
- Duration: 3 months
- Schedule: 2–3 times per week
- Daily Session Length: 2 hours
- Format: Practical training with real engineering tasks
- Participants will gain hands-on experience by working on real engineering tasks under professional guidance
Program Stages
- Submit your application for the course
- Complete the offline test
- Participate in the interview
- Enroll in the training program
- Undergo assessments after each session to monitor progress
- Complete the final evaluation
Top graduates who successfully complete the program will be invited to join Grovf’s engineering team.
If you are eager to dive deeper into hardware/software co-design systems and work with cutting-edge technologies, we encourage you to apply.
Send your CV to https://grovf.spark.work/career/job/3/application?isTracked=true
Application deadline: 18.01.2026
Program start: February First Week, 2026
