Sofics

Name: Sofics
Address: Sint-Godelievestraat 32, Aalterburg, 9880, BE
Telephone: +3292168333

Als Vlaamse KMO ontwerpen, testen en patenteren we elektronische circuits om de ICs van onze internationale klanten te beschermen tegen ESD.

20/08/2026

Intern Spotlight: Stan

Stan’s current project focuses on two key areas:
1️⃣ The design of a proprietary voltage regulator and testing its compatibility for use in an ESD rail clamp.
2️⃣ A comparative study between our proprietary design and a standard regulator to identify key industry-standard specifications.

18/08/2026

Celebrating a major milestone!
We are so proud to celebrate Sven’s 20th work anniversary. Two decades of dedication is a massive achievement and we couldn't let the day pass without a little fun.
Before heading out for a celebratory lunch, the team put Sven to the test with a "Sventelligence" quiz, covering everything from classic board games to modern video games.
As some of you may know, Sven is our resident gaming expert and he certainly did not disappoint!

Congratulations on 20 incredible years, Sven! We are so lucky to have you on the team.

13/08/2026

During a recent 6-week internship at Sofics, Ceres van Nuffel conducted research into DPI LIN clamp assessment.

The internship focused on utilizing TLP and DPI setups to analyze how ESD devices influence DPI performance. A key objective of the study was to investigate whether a clear correlation exists between TLP and DPI measurement data.

11/08/2026

HOT CHIPS is THE place where IC designers present their latest work on high performance compute and AI chips on the most advanced process nodes.
Bart Keppens wants to check out what top companies like Nvidia, AMD, Broadcom, Meta, Cerebras are working on.

He hopes to hear about the reliability issues they are facing.
Sofics may be able to help with proven specialty I/O and ESD protection down to 2nm.

More info on the conference:
- https://hotchips.org/
- From Sunday, August 23 till Tuesday, August 25, 2026
- Memorial Auditorium, Stanford, Palo Alto, CA.

06/08/2026

High-speed and ESD design teams often work separately, even though both sides influence the same interface.

That can lead to conflicting design constraints, duplicated components and compromises in power, performance, area and robustness.

This internship focuses on investigating where the two designs overlap. Can components be shared? Can an optimization in the high-speed circuit reduce the burden on the ESD protection? Can a protection concept be integrated without limiting signal performance?

The goal is to identify practical co-design opportunities that help both sides of the interface, rather than optimizing them in isolation.

A good example of the kind of real design challenge our interns work on at Sofics.

04/08/2026

Project management isn't a default, it's a decision, and knowing when to make it is a skill on its own.
That was one of the first things Arno Stockman made clear during our most recent Lunch & Learn.
Sometimes all a task needs is a clear owner and deadline rather than a complete PM structure.

We put our minds together and applied project management to the opening of a (fictional) restaurant called Sof-Eats.
Budget, licenses, staff, timing all fighting for attention. A good way to see where a project manager really makes a difference!

Even though we were able to apply proper project management, we have decided to stick with what we know best and are leaving the restaurant as a fictional concept.

30/07/2026

Mathias has spent his time with us this summer in the lab, not behind a desk.

He's been running ESD measurements on one of our FinFET test chips, helping verify how our solutions hold up in one of the more popular FinFET nodes. That's not a small task. FinFET brings its own set of challenges for ESD design, and getting clean, reliable data matters.

He's also run TLP and DC testing, checking that our clamps still perform the way they should after a process update. Small changes in a process can shift device behavior in ways that aren't always obvious until you test for it.

Good, careful measurement work like this is what keeps our IP dependable across nodes and process revisions. Glad to have had Mathias contributing to it.

27/07/2026

A single stray particle can destroy a chip. That's daily life for the electronics we talked about at last year's TSMC OIP Forum. Chips that sit inside nuclear reactors, ride on satellites and work next to particle beams.

Together with Magics Technologies , we presented how we keep those chips alive. Magics builds the radiation-hardened core in standard CMOS. It tolerates up to 100 Mrad of total dose. That's about a thousand times a typical commercial chip. Sofics builds the ESD protection on every pad. It has to survive that same radiation without slowing the signal down.

One example from the talk: cold-spare interfaces on satellites. An unpowered backup chip still sees signals on its I/O and can't leak into a dead supply rail. Standard ESD diodes don't work there. So we built a clamp that protects the pin without ever touching the dead rail.

That combination now runs in ITER's fusion systems, on satellites or on a rover currently driving around Mars.

A good example of what two Belgian companies can build together on the same TSMC platform when the stakes are as real as it gets.

Read the article here: https://monthly-pulse.com/2026/07/28/radiation-hardened-by-design-building-interfaces-for-space-and-nuclear-on-tsmc-cmos/

Adres

Sint-Godelievestraat 32
Aalterburg
9880

Telefoon

+3292168333

Website

https://linktr.ee/sofics

Meldingen

Wees de eerste die het weet en laat ons u een e-mail sturen wanneer Sofics nieuws en promoties plaatst. Uw e-mailadres wordt niet voor andere doeleinden gebruikt en u kunt zich op elk gewenst moment afmelden.