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Monday 9am - 5pm Tuesday 9am - 5pm Wednesday 9am - 5pm Thursday 9am - 5pm Friday 9am - 5pm

Silvaco

Name: Silvaco
Address: 4701 Patrick Henry Drive, Building 23, Santa Clara, CA, 95054, US
Telephone: +14085671000
Price range: $$

Silvaco, Inc. is a leading EDA provider of software tools used for TCAD to Signoff and also production-proven intellectual property (IP) cores.

05/28/2026

Join Silvaco's CEO, Wally Rhines at the ESD Alliance Executive Outlook, June 10, 2026.

As agentic AI moves from buzzword to blueprint, the semiconductor industry is at an inflection point—and the executives navigating it firsthand will take the stage at the ESD Alliance Executive Outlook.

Leaders from established EDA companies and emerging agentic AI startups come together to get into the details—examining what's genuinely changing in chip design and verification, where collaboration between traditional EDA and the new wave of AI companies is creating real momentum, and what these shifts mean for the broader landscape.

HURRY REGISTER NOW! Discover how the EDA industry is shifting back-to-back events this June with the ESD Alliance. Learn about the impact of agentic AI at the Executive Outlook on June 10 in San Jose, followed by our FREE Exports Webinar on June 11. Register for both events today

➡️ https://semiamericas.org/esda-executive-outlook-2026

05/27/2026

Accelerate GAA-NS-FET Design with Full-Device Quantum Transport Simulation

There is still time to register for our webinar “Fast and Integrated Quantum Transport Solution for GAA-NS-FET Design Exploration & Optimization at Full-Device Scale” given by [Philippe Blaise].

👉 Register here:

https://silvaco.com/webinar/fast-and-integrated-quantum-transport-solution-for-gaa-ns-fet-design-exploration-optimization-at-full-device-scale/

We demonstrate how Victory Atomistic, seamlessly integrated with Silvaco’s leading AI-powered FTCO™ workflow, forms a fast and integrated quantum transport solution which enables rapid prototyping as well as design exploration and optimization of GAA-NS-FETs — including key figures of merit such as DIBL, Vth, SS, and injection velocity — across a wide range of geometries, materials, and temperatures.

✅ What you’ll learn:

Why quantum transport simulation using NEGF is essential

How Victory Atomistic achieves fast simulation turnaround times and high fidelity

How to set up and run a GAA-NS-FET simulation end-to-end

How Victory Atomistic can be used in familiar device optimization and FTCO workflows

05/21/2026

Accelerate GAA-NS-FET Design with Full-Device Quantum Transport Simulation

Join us June 4th for our webinar “Fast and Integrated Quantum Transport Solution for GAA-NS-FET Design Exploration & Optimization at Full-Device Scale” given by Philippe Blaise.

👉 Register here:

https://silvaco.com/webinar/fast-and-integrated-quantum-transport-solution-for-gaa-ns-fet-design-exploration-optimization-at-full-device-scale/

We demonstrate how Victory Atomistic, seamlessly integrated with Silvaco’s leading AI-powered FTCO™ workflow, forms a fast and integrated quantum transport solution which enables rapid prototyping as well as design exploration and optimization of GAA-NS-FETs — including key figures of merit such as DIBL, Vth, SS, and injection velocity — across a wide range of geometries, materials, and temperatures.

✅ What you’ll learn:
• Why quantum transport simulation using NEGF is essential
• How Victory Atomistic achieves fast simulation turnaround times and high fidelity
• How to set up and run a GAA-NS-FET simulation end-to-end
• How Victory Atomistic can be used in familiar device optimization and FTCO workflows

05/20/2026

Join Silvaco at the TSMC 2026 Europe Technology Symposium on May 28th!

Silicon innovation is expanding AI to infinite possibilities. Visit us at the Ecosystem Pavilion to explore our latest breakthroughs in design tools and discover how our collaboration with TSMC empowers your AI innovations. We look forward to meeting you there!

For more information, please visit: https://www.tsmc.com/static/english/campaign/Symposium2026/index.htm

05/19/2026

Silvaco is pleased to announce the immediate availability of Mixel MIPI C‑PHY/D‑PHY Combo IP on the TSMC N2P process.

This next-generation solution is the industry’s first to support MIPI D‑PHY v3.6 with embedded clock mode (ECM), enabling high-speed performance while reducing power consumption, leakage, and area.

Key features include:

• Support for MIPI C‑PHY v2.1 and D‑PHY v3.6
• Embedded clock mode (ECM) for improved efficiency
• Up to 3.0 Gbps per lane in high speed D-PHY ECM mode
• Up to 3.0 Gsps per lane in high speed C-PHY mode
• 25% fewer wires compared to forwarded-clock implementations of C-PHY/D-PHY combo IP
• Optimized for low power, minimal area, and advanced-node designs

Designed for applications such as AR glasses, wearables, and next-generation SoCs, this solution addresses extreme form factor and performance requirements.

👉 Read the full announcement:

https://investors.silvaco.com/news-releases/news-release-details/silvaco-announces-immediate-availability-mixel-mipi-c-phyd-phy

-PHY -PHY

05/06/2026

Join Silvaco at Booth 13 at the TSMC 2026 Taiwan Technology Symposium on May 14th!

Silicon innovation is expanding AI to infinite possibilities. Visit us at the Ecosystem Pavilion to explore our latest breakthroughs in design tools and discover how our collaboration with TSMC empowers your AI innovations. We look forward to meeting you there!

For more information, please visit: https://www.tsmc.com/static/english/campaign/Symposium2026/index.htm

04/28/2026

Accelerating Next-Generation Power Technologies with AI-Powered FTCO

The power semiconductor industry is at an inflection point. For over three decades, silicon has served as the workhorse material for power electronics, but the relentless push towards higher power densities, faster switching frequencies, and greater efficiency is driving a decisive shift to wide bandgap (WBG) materials. Silicon carbide (SiC) and gallium nitride (GaN) are now firmly established as the technologies of choice for next-generation power applications, spanning electric vehicles (EVs), artificial intelligence (AI) data center infrastructure, and grid-connected renewable energy systems.

In our latest Simulation Standard we examine how Silvaco’s AI-powered Fab Technology Co-Optimization (FTCO™) platform, combining simulation at scale, smart Design of Experiments (DOE), and machine learning (ML) surrogate models, is transforming the power device development workflow, with practical demonstrations on pGaN HEMTs, vertical GaN, and SiC DMOS technologies.

Highlights:

• FTCO accelerates device calibration and optimization
• FTCO surrogate models deliver real-time predictions
• Fast manufacturability and yield assessment before fabrication
• Dyna•ic device behavior captured with high fidelity

Showcases: pGaN HEMT, vertical GaN, and SiC DMOS

📄 Read the full Simulation Standard here:

https://silvaco.com/simulation-standard/accelerating-next-generation-power-technologies-with-ai-powered-ftco/

04/27/2026

Last Chance to register for our webinar: Accelerating Next Generation Power Technologies

This webinar introduces Silvaco’s AI powered Fab Technology Co-Optimization (FTCO™) approach for accelerating next generation power technology design workflows, which combines simulation at scale, smart DOE, and machine learning surrogate models to create physics based digital twins of devices and processes. Through case studies—including pGaN HEMTs, vertical GaN, and SiC DMOS technologies—we demonstrate how calibrated TCAD models and ML surrogates enable rapid optimization, variability analysis, and yield prediction while significantly reducing development cycles and physical DOE cost.

📅 April 30, 2026

What You Will Learn:

🔹 Wide bandgap power market overview

🔹 FTCO accelerates design workflows

🔹 AI powered calibration, optimization and digital twins

Attendees will gain practical insight into how digital twins and parallel simulation workflows are transforming power device design, from early technology pathfinding through manufacturing support and application level validation.

🎟️ Register:

https://silvaco.com/webinar/accelerating-next-generation-power-technologies/

04/22/2026

There is still time to register for our webinar: Accelerating Next Generation Power Technologies

This webinar introduces Silvaco’s AI powered Fab Technology Co-Optimization (FTCO™) approach for accelerating next generation power technology design workflows, which combines simulation at scale, smart DOE, and machine learning surrogate models to create physics based digital twins of devices and processes. Through case studies—including pGaN HEMTs, vertical GaN, and SiC DMOS technologies—we demonstrate how calibrated TCAD models and ML surrogates enable rapid optimization, variability analysis, and yield prediction while significantly reducing development cycles and physical DOE cost.

📅 April 30, 2026

What You Will Learn:

🔹 Wide bandgap power market overview

🔹 FTCO accelerates design workflows

🔹 AI powered calibration, optimization and digital twins

Attendees will gain practical insight into how digital twins and parallel simulation workflows are transforming power device design, from early technology pathfinding through manufacturing support and application level validation.

🎟️ Register:

https://silvaco.com/webinar/accelerating-next-generation-power-technologies/

04/21/2026

We're proud to share that Keith Odland, Director of Product Marketing for Silvaco's Semiconductor IP Business Unit, will be speaking at D&R IP-SoC Silicon Valley 2026 — the premier worldwide spring event dedicated to Silicon IP and IP-based electronic systems.

As part of the Design and Verification Platform track, chaired by Dagmara Zielinska of Design & Reuse, Keith will present:

"Practical Considerations for Choosing a Production Ready Offering (PRO) IP Over a Fully Customized Solution"

His session will unpack the real-world tradeoffs design teams face when deciding between proven, production-ready IP and fully custom alternatives — covering time-to-market, risk, cost, and long-term scalability.

If you're attending, come connect with Keith and the Silvaco team to discuss how our IP portfolio is helping SoC designers accelerate innovation.

April 23rd, 2026

Hyatt Regency Santa Clara
Design and Verification Platform Track
5:00pm

More information:

https://www.design-reuse-embedded.com/ipsocdays/2026/SiliconValley/

Address

4701 Patrick Henry Drive, Building 23
Santa Clara, CA
95054

Opening Hours

Monday	9am - 5pm
Tuesday	9am - 5pm
Wednesday	9am - 5pm
Thursday	9am - 5pm
Friday	9am - 5pm

Telephone

+14085671000

Website

http://www.silvaco.com/

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